1. Field of the Invention
The present invention relates to a test apparatus and test method. In particular, the present invention relates to a test apparatus and test method for detecting delay faults of a circuit.
2. Related Art
In recent years, improved fine processing technology for LSIs has promoted reduction in the size of logic device components included within LSIs. This leads to reduction in the driving performance of the logic device components, resulting in delay faults of the logic device components, which are the primary factor involved in faults of these logic device components.
Non-Patent Documents 1 through 4 listed below disclose scan methods in which high-speed switching of the test pattern, from that at a predetermined cycle to that at another cycle, is performed in order to perform a scan test regarding whether or not delay faults have occurred.
With the methods disclosed in Non-Patent Documents 1 through 4, the clock interval of adjacent clocks (double clocks) is controlled in order to test whether or not a circuit operates properly. This enables detection to be made regarding whether or not the circuit operates within a predetermined delay time.
(1) Non-Patent Document 1
J. P. Hurst, N. Kanopoulos, “Flip-Flop Sharing in Standard Scan Path to Enhance Delay Fault Testing of Sequential Circuits”, Asian Test Symposium, Nov. 23, 1995, IEEE, pp. 346-352.
(2) Non-Patent Document 2
K. Hatayama, M. Ikeda, M. Takakura, S. Uchiyama, Y. Sakamoto, “Application of a Design for Delay Testability Approach to High Speed Logic LSIs”, Asian Test Symposium, Nov. 17, 1997, IEEE, pp. 112-115.
(3) Non-Patent Document 3
N. A. Touba, E. J. McCluskey, “Applying Two-Pattern Tests Using Scan-Mapping”, IEEE VLSI Test Symposium 1996, Apr. 28, 1996, IEEE, pp. 393-397.
(4) Non-Patent Document 4
Eric MacDonald, N. A. Touba, “Delay Testing of SOI Circuits: Challenges with the History Effect”, International Test Conference 1999, Sep. 27, 1999, IEEE, pp. 269-275.
(5) Non-Patent Document 5
Hiroyuki Mizuno, “Increase of Leak Current Accompanying Low voltage and High-Speed of CMOS LSI and a Technique for Reducing the Leak Current”, The Transactions of the Institute of Electronics, Information and Communication Engineers, Vol. J83-C, No. 10, October 2000, pp. 926-935.
With the above-described test using such a double clock, delay faults are detected by controlling the clock interval. However, there are limits to the precision with which the clock interval can be set. This leads to difficulty in fine detection of delay faults.
Also, with the above-described test which uses such a double clock, the absolute value of the delay time is measured for the circuit, and determination is made whether or not the LSI is acceptable based upon the absolute value thus measured.
Accordingly, such methods have the disadvantage that determination cannot be made whether the delay thus measured is due to irregularities in the operations of the logic device components or due to delay faults of a particular logic device component.